Mr. Mehdi Tabei

Department

Personal Information

Mr. Mehdi Tabei

Academic Rank: Instructor

Tel: 031-36862170 local: 129

Email: tabei@shbu.ac.ir

Educational Background

B.Sc.

Computer Engineering_Hardware, Shahid Bahonar, Kerman, Iran, 2006

M.Sc.

Computer Systems Architecture, Isfahan, Isfahan, Iran, 2013

Areas of Interest

Computer Architecture

Computer Networks

VLSI

Journals paper

2017/23/1
  • 1  Seyed Mohammad Mahdi Tabei-Hooman Nikmehr. An unsigned truncated sequential multiplier with variable error compensation. Elsevier. Microprocessors and Microsystems. 49 link
2018/9/3
  • 2  Maede Jabbar Zare-Hossein Mohammadi Nejad-Seyed Mohammad Mahdi Tabei. An Approximate Multiplier-Accumulator Based on Radix-4 Modified Booth Algorithm. IOSR Journal of Engineering (IOSRJEN). IOSR Journal of Engineering (IOSRJEN). 8 link

Conferences paper

2012/11/7
  • 1  Seyed Mohammad Mahdi Tabei-Hooman Nikmehr. A TRUNCATED SEQUENTIAL MULTIPLIER WITH DYNAMIC ERROR COMPENSATION. National Congress of Electrical, Computer and Information Technology Engineering . PP.1781-1786. Khayyam University, Mashhad, Iran. link
2015/12/17
  • 2  Marzieh Fathi-Seyed Mohammad Mahdi Tabei-Hooman Nikmehr. Improving the Precision of Truncated Floating Point Multiplication Through Carry Digit Estimation. National Conference on Axial Development of Civil Engineering, Architecture, Electrical and Mechanical Engineering of Iran. 2. Golestan University, Gorgan, Iran. link

Courses

Logical Circuits

Computer Architecture

Microprocessor

Data Communications

Interface Circuits

Digital Systems Automated Design (VHDL)

Logical Circuits Laboratory

Computer Architecture Laboratory

Microprocessor Laboratory

Digital Electronic

Digital Electronic Laboratory

VLSI

Fundamentals of Digital Electronic

Signals and systems

Embedded and real time systems

Specialized Language

Computer Laboratory

Computer Application in Management

advanced Logical Circuits

Digital Systems

Digital Systems

Linear Control

Master Thesis

Row Title Colleagues Defense Date
1  
An estimating 64-bit sequential multiplier with progressive accuracy
Seyed Mohammad Mahdi Tabei
2013/15/1